1. Technical Field of the Invention
This invention pertains to random access memory cells. In particular, this invention pertains to testing the performance characteristics of individual memory cells, thereby providing specific performance data typically unavailable in mass integration testing schemes.
2. Description of the Prior Art
The building block of today""s high-density DRAM chips is one provided with a single transistor cell. FIG. 1A shows the design of a conventional DRAM cell that uses a trench as Node Capacitor (NC) and a vertical NMOSFET, as the transfer device. In this design, XA and Buried Strap (BS) junctions and the vertical gate oxide formed along the top trench make up the vertical transfer device. The gate oxide is controlled by Word Line (WL), while Bit Line (BL) is used to transfer charge to NC. The charge transfer between Bit Line (BL) and NC occurs by inverting the channel of the transfer device (WL high) and adequately biasing BL (V(BL) greater than 0). In this case, a logic 1 is stored in NC by transferring electrons from NC to BL, while a 0 is stored by transferring electrons from BL to NC. The 1 or 0 status is maintained in the storage capacitor by accumulating the channel (WL low). The DRAM cell is isolated by conveniently biasing PWELL (PW) and buried plate (BP). FIG. 1B illustrates a circuit schematic of the DRAM cell shown in FIG. 1A. A key feature of this structure is that the BS junction is directly connected to NC and is not directly addressable.
A careful evaluation of the transfer and retention of charge capabilities is critical in the early phases of the cell development. Typically, this is achieved by circuit simulation. HCspice DC Array device models are, for example, developed from measuring the. DC Array device parameters, using them to characterize the storage and transient characteristics of the cell. These simulations are confirmed later when a product is available for testing. This approach has two inherent problems: 1) appropriate structures need to be designed for a direct probing of BS and DC characterization of the transfer device, and 2) the product test may come too late in the cell development, making it very difficult to (retroactively) optimize the cell design. It is desirable to test different cell designs, and readjust parameters of the cell, such as trench parameters, buried strap engineering, implants, oxide thickness, etc., at given voltages and temperatures.
One of the problems that exists in memory cell development during qualification activities for any trench based DRAM, is that it is not easy to stress the arrays in a real world memory environment. Most of the work that is done is at production level (burn-in, etc.). Burn-in is where, for example, a 250 megabit memory is provided and 250 million cells are exercised altogether. By doing so, certain circuit parameters, such as retention time and the like are tracked, particularly those that somehow are indirectly related to the actual cell operation. However, there is no previously known way to directly stress a cell with controlled inputs and sense the response of the single device cell in a real environment. Today, memory technologies develop the design on the production level, i.e., with millions of cells exercised by a process diagnostic monitor, by stressing them altogether. The array device features and sensitivities are thereby quantified indirectly. The present invention allows testing and stressing of the array device and cell to be performed directly rather than on a mass integration level.
Further, no method has been previously developed to directly measure the transfer and storage of charge in a realistic structure without a recurring product test. The prior art does not provide a circuit for directly measuring charge transfer/retention characteristics in DRAM one transistor cells. Neither does the prior art solve the problem on how to run key device DC reliability stresses on particular production cell structures and establish their impact on EOL (End of Life) projections.
The present invention provides a circuit that fundamentally probes a device in a network (directly stress) and senses the charge transfer characteristics. Eventually, each of the 250 million cells can be tested, as mentioned in the example above, but herein a direct link to one or a group of devices must be established. By selecting the bitline and wordline for each, one can run a product stress and investigate a single cell fail. It is now possible to electrically sense a single cell by focusing directly on the cell to stress it. Finally, one can also characterize the device of any cell in any environment to see if weak cells are present.
By exercising a DRAM cell device with a known time within which the cell stores a charge, the amount of charge stored, the length of time when most of the charge is retained and voltage is applied, one can generate and use this information by sending pulses to the cell in a way that one can characterize the charge transfer itself. This methodology can be used not only for testing charge transfer characteristics, but also for stressing the cell to perform lifetime wearout modeling.
The DRAM application described hereinafter is an example of how this process and circuit can be applied to characterize any charge transfer device in its production environment.
In a first aspect of the invention, there is provided a DRAM cell as part of an circuit whose basic elements are a MOSFET device connected in series with a capacitor used as a charge transfer device (FIG. 1C). MOSFET junction (3) (equivalent to BS) is connected to the capacitor and is not directly addressable. The charge exchange between capacitor (NC) and junction (1) takes place by modulating gate (2). It is of critical importance to characterize the charge retention and transfer of the capacitor and the MOSFET device, respectively. Since the junction (3) cannot be directly addressable this cannot be achieved by simple DC testing.
In a second aspect of the invention, there is provided a methodology as well as an on-chip circuit for characterizing the charge retention and transfer response of the basic circuit, as illustrated in FIG. 1C, using a realistic test sequence. Although this methodology can be used for this general structure, it will be described by using the vertical DRAM cell (shown in FIG. 1A).
Accordingly, it is an object of the invention to provide a new on-chip circuit and testing methodology that allow quantifying the transistor charge transfer and the NC charge storage capability of a DRAM cell in a realistic field environment.
It is another object of the invention to provide an on-chip circuit that imposes and senses a voltage in an individual DRAM storage capacitor.
It is still another object of the invention to provide a pulse test method to characterize an individual storage capacitor charge leakage rate while the wordline is at low and when a logic 1 is initially stored in the DRAM cell.
It is yet another object of the invention to provide a test method for quantifying the rate of charge transfer between the bitline and the storage capacitor in an individual DRAM cell.